Microelectronic assemblies generally include one or more ICs, such as for example one or more packaged dies (“chips”) or one or more dies. One or more of such ICs may be mounted on a circuit platform, such as a wafer such as in wafer-level-packaging (“WLP”), printed board (“PB”), a printed wiring board (“PWB”), a printed circuit board (“PCB”), a printed wiring assembly (“PWA”), a printed circuit assembly (“PCA”), a package substrate, an interposer, or a chip carrier. Additionally, one IC may be mounted on another IC. An interposer may be an IC, and an interposer may be a passive die or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device. Furthermore, an interposer may be formed like a PWB, namely without any circuit elements such as capacitors, resistors, or active devices. Additionally, an interposer includes at least one through-substrate-via.
An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs. An IC may be coupled to a circuit platform by bonding, such as bonding traces or terminals, for example, of such circuit platform to bond pads or exposed ends of pins or posts or the like of an IC. Additionally, a redistribution layer (“RDL”) may be part of an IC to facilitate a flip-chip configuration, die stacking, or more convenient or accessible position of bond pads for example.
An IC die or an interposer may be coupled to traces or terminals, so a packaged microelectronic element may be mounted to a circuit panel by bonding traces or terminals of such circuit panel to contacts, such as contact pads for example, on such IC die or interposer. For example, some IC dies and some interposers used in microelectronic packaging have terminals in the form of exposed ends of pins or posts extending through a dielectric layer. In other applications, terminals of an IC die or interposer may be externally accessible pads or portions of traces formed on an RDL.
Conventionally, via structures, including without limitation, through-silicon vias (“TSVs”) have had a dielectric liner capacitance causing frequency-dependent signal attenuation (“signal loss”). More particularly, low frequency signals passed through such vias with little signal loss in comparison to high frequency signals. Such signal loss degraded performance of high-speed applications, including without limitation in stacked die assemblies with cascaded TSVs. Along those lines, a signal “eye” conventionally had a significant amount of jitter due to such difference between low and high frequency signal loss.
Accordingly, it would be desirable and useful to reduce signal eye jitter.